This application claims the benefit of Korean Patent Application No. 98-30869, filed on Jul. 30, 1998, which is hereby incorporated by reference.
1. Field of Invention
The present invention relates to a thin film transistor and a fabricating method thereof wherein the source and drain wires are located at the lowest layer on a substrate and a double gate structure is provided.
2. Discussion of Related Art
Compared to an amorphous silicon thin film transistor (hereinafter abbreviated TFT), a polycrystalline silicon TFT has a high mobility of electrons and holes and can be used as a CMOS TFT. Accordingly, a liquid crystal display (hereinafter abbreviated LCD) having polycrystalline silicon TFTs has a structure such that both a driver and a pixel array are formed on a glass substrate.
When polycrystalline silicon TFTs are formed in a driver, an LCD permits switching operations at a fast frequency due to the characteristics of polycrystalline silicon. Yet, when polycrystalline silicon TFTs are fabricated on a pixel array in an LCD, the characteristics of the image deteriorates due to the high drain current during off-states due to the characteristics of polycrystalline silicon.
More recently, in order to reduce the off-current in a pixel array to a proper level, TFTs having a lightly doped drain (LDD) structure, an offset structure or the like have been used.
FIG. 1 shows a schematic cross-sectional view of a TFT according to a related art. Referring to FIG. 1, source and drain wires are formed on a substrate, a buffer layer for crystallizing silicon covers the source and drain wires and an exposed surface, and a TFT of a coplanar type is formed on an insulating layer. This structure is called a buried bus coplanar (BBC) structure.
Source and drain electrodes 11S and 11D are formed on an insulated substrate 100, and a first insulating layer 12 covers an exposed surface of the substrate. A channel region 13C, LDD regions 13L and source and drain regions 13S and 13D, which are formed with polycrystalline silicon, are formed on predetermined areas of the first insulating layer 12.
A gate insulating layer 14 and a gate electrode 15 are formed on the active layer 13. The gate insulating layer 14 on the active layer 13 overlaps the LDD regions 13L and the channel region 13C, and the gate electrode 15 on the gate insulating layer 14 lies over the channel region 13C of the active layer 13.
A second insulating layer 16 covers the above structure on the substrate. Contact holes exposing the source and drain electrodes 11S and 11D on the insulated substrate 100 and the source and drain regions 13S and 13D in the active layer are formed in the second insulating layer 16. A first interconnection wire 17-1 connecting the source electrode to the source region 13S and a second interconnection wire 17-2 connecting the drain electrode 11D to the drain region 13D are formed on the second insulating layer 16.
When a TFT having the above structure is applied to the fabrication of an LCD, TFTs located in the pixel array and the circuit part are fabricated simultaneously. Thus, structures of TFTs in the circuit part may be fabricated to have LDD regions of the same quality as those in the pixel array.
However, when TFTs of the above structure are used for the devices in a driver, the on-current is reduced due to the location of LDD regions in the active layer. Accordingly, operation speed of the driver becomes slower as the current driving capacity of the driver drops.
Moreover, as a high voltage between the source and the drain is applied to TFTs in a driver to generate a high electrical field in a drain region, degradation is caused by increasing numbers of hot carriers. Thus, device characteristics deteriorate.
Accordingly, the present invention is directed to a thin film transistor and a fabricating method thereof that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a thin film transistor and a fabricating method thereof, wherein the transistor has a BBC structure, which means that source and drain electrodes are on a substrate, and lightly-doped (LD) regions of low resistance and improved current driving capacity reduces the degradation of a device.
Another object of the present invention is to provide an liquid crystal display and a fabricating method thereof, wherein a driver uses TFTs which have improved current driving capacity and reduced degradation of devices and a pixel array uses TFTs where the off-current is reduced. Accordingly, the driver has a fast operating speed and the pixel array has excellent device characteristics.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes a substrate, a source electrode, a drain electrode and a lower gate electrode on the substrate, a buffer layer covering an exposed surface of the substrate including the source, drain and lower gate electrodes, an active layer on the buffer layer wherein a source region, a drain region, LD regions and a channel region are formed in the active layer, a gate insulating layer on the channel and LD regions, an upper gate electrode on the gate insulating layer over the channel region, a passivation layer covering the upper gate electrode, a plurality of contact holes in the buffer and passivation layers, wherein the contact holes expose the source and drain electrodes and the source and drain regions, a first interconnection wire connecting the source electrode to the source region, and a second interconnection wire connecting the drain electrode to the drain region.
In one embodiment, the present invention includes a substrate, a source electrode and a drain electrode on the substrate, a buffer layer covering an exposed surface of the substrate including the source and drain electrodes, an active layer on the buffer layer wherein a source region, a drain region, LD regions and a channel region are formed in the active layer and wherein the drain region and the LDD region inside the drain region are overlapped with the drain electrode, a gate insulating layer on the channel and LD regions, an upper gate electrode on the gate insulating layer over the channel region, a passivation layer covering the upper gate electrode, a plurality of contact holes in the buffer and passivation layers wherein the contact holes expose the source and drain electrodes and the source and drain regions, a first interconnection wire connecting the source electrode to the source region, and a second interconnection wire connecting the drain electrode to the drain region.
In another embodiment, the present invention includes the steps of forming a source electrode, a drain electrode and a lower gate electrode on a substrate, forming a buffer layer on the substrate as well as on the source, drain and lower gate electrodes, forming an active layer on the buffer layer over the lower gate electrode, depositing a gate insulating layer and a conductive layer on an exposed surface of the surface as well as on the active layer, defining a photoresist pattern for a gate formation on the conductive layer, forming an upper gate electrode by overetching the conductive layer using the photoresist pattern as a mask, anisotropically etching the gate insulating layer using the photoresist pattern as a mask, removing the photoresist pattern, forming a source region, a drain region and LD regions by doping the active layer with impurities using the upper gate electrode and the gate insulating layer as masks, forming a passivation layer covering an exposed surface of the substrate including the upper gate electrode, forming a plurality of contact holes in the buffer and passivation layers, wherein the contact holes expose the source and drain electrodes and the source and drain regions, and forming a first interconnection wire connecting the source electrode to the source region and a second interconnection wire connecting the drain electrode to the drain region.
In another embodiment, the present invention includes the steps of forming a source electrode and a drain electrode on a substrate, forming a buffer layer covering the substrate as well as on the source, drain and lower gate electrodes, forming an active layer on the buffer layer overlapped with the lower gate electrode, depositing a gate insulating layer and a conductive layer each on an exposed surface of the surface as well as on the active layer, defining a photoresist pattern for a gate formation on the conductive layer, forming a gate electrode by overetching the conductive layer using the photoresist pattern as a mask, anisotropically etching the gate insulating layer using the photoresist pattern as a mask, removing the photoresist pattern, forming a source region, a first LD region inside the source region, a drain region overlapped with the drain electrode and a second LD region by doping the active layer with impurities using the gate electrode and the remaining gate insulating layer as masks, forming a passivation layer covering an exposed surface of the substrate as well as the gate electrode, forming a plurality of contact holes in the buffer and passivation layers, wherein the contact holes expose the source and drain electrodes and the source and drain regions, and forming a first interconnection wire connecting the source electrode to the source region and a second interconnection wire connecting the drain electrode to the drain region.
In another embodiment, the present invention includes a substrate, a first thin film transistor, the first thin film transistor further comprising: a source electrode and a drain electrode on the substrate; a buffer layer covering an exposed surface of the substrate as well as the source and drain electrodes; an active layer on the buffer layer, wherein a source region, a drain region, LD regions and a channel region are formed in the active layer; a gate insulating layer on the channel and LD regions; and a gate electrode on the gate insulating layer over the channel region, a second thin film transistor, the second thin film transistor further comprising: a source electrode, a drain electrode and a lower gate electrode on the substrate; a buffer layer covering an exposed surface of the substrate as well as the source, drain and lower gate electrodes; an active layer on a predetermined portion of the buffer layer, wherein a source region, a drain region, LD regions and a channel region are formed in the active layer; a gate insulating layer on the channel and LD regions in the active layer; and an upper gate electrode on the gate insulating layer over the channel region, a passivation layer covering the first and second thin film transistors, a plurality of contact holes exposing the source and drain electrodes and the source and drain regions in the first and second thin film transistors, a pixel electrode connecting the drain electrode to the drain region of the first thin film transistor, a first interconnection wire connecting the source electrode to the source region in the second thin film transistor, and a second interconnection wire connecting the drain electrode to the drain region.
In another embodiment, the present invention includes the steps of defining a pixel array and a driver on a substrate, forming a source electrode and a drain electrode on the substrate in the pixel array and forming a source electrode, a drain electrode and a lower gate electrode on the substrate in the driver, forming a buffer layer covering an exposed surface of the substrate as well as the lower gate electrode, forming an active layer of the pixel array and an active layer of the driver on the buffer layer, depositing a gate insulating layer and a conductive layer in a single pump down on an exposed surface of the substrate as well as on the active layers, defining a photoresist pattern for a gate formation on the conductive layer, forming a gate electrode of the pixel array and an upper gate electrode of the driver by overetching the conductive layer using the photoresist pattern as a mask, anisotropically etching the gate insulating layer using the photoresist pattern as a mask, removing the photoresist pattern, forming source regions, LD regions, drain regions by doping the active layers in the pixel array and the driver with impurities using the gate electrode of the pixel array, the upper gate electrode of the driver and the remaining gate insulating layer as masks, forming a passivation layer covering an exposed surface of the substrate as well as the gate electrode of the pixel array and the upper gate electrode of the driver, forming a plurality of contact holes in the buffer and passivation layers, wherein the contact holes expose the source and drain electrodes of the pixel array and the source and drain electrodes and the source and drain regions of the driver, and forming a pixel electrode connecting the drain electrode to the drain region, a first interconnection wire connecting the source electrode to the source region of the driver and a second interconnection wire connecting the drain electrode to the drain region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.